Syllabus
Lecture Slides
VHDL Shift Register Model
Two Page VHDL Reference
Five Page VHDL Reference
Seventeen Page VHDL Reference
Homework Assignments
Homework #1
#2:Due 2/3/04 1.8a(10), 1.8b(10), 1.10a(10), 1.10b(10), 3.2a(10), 3.2b(10), 3.2c(10), 3.3a(15), 3.3b(15)
#3:Due 2/19/04 2.2(25), 2.5(25), 2.7(25), 2.9(25)
#4: Due 3/16/04 8.1(25), 8.2(25), 8.4(25), 8.6(25)
#5: Due 4/15/04 5.1(20), 5.6(a)(10), 10.1(25), 10.3(25), 10.7(20)
Laboratory Assignments
Lab #1
Lab #2
Lab #3
Lab #4
Graduate Design Project
Homework Solutions
Homework #1 Part 1
Homework #1 Part 2
Homework #2
Homework #3
Homework #4
Homework #5
Test and Solutions
CPE/EE 422/522 Midterm
CPE/EE 422/522 Midterm Solution
CPE/EE 422/522 Sample Final
CPE/EE 422/522 Final Exam
CPE/EE 422/522 Final Exam Solution
Announcements
grubbs@eng.uah.edu