-- This is a behavioral model of a Mealy state machine based on
-- its state table.  The output (Z) and next state are computed 
-- on the rising edge of the clock OR when the input (X) changes.
-- The state change occurs on the rising edge of the clock.  

library BITLIB;
use BITLIB.Bit_pack.all;

entity SM1_2 is   
    port(X, CLK: in bit;
         Z: out bit);
end SM1_2;

architecture Table of SM1_2 is   
    signal State, Nextstate: integer := 0;
begin   
    process   
    begin   
	case State is      
            when 0 =>         
                if X='0' then Z<='1'; Nextstate<=1; end if;
                if X='1' then Z<='0'; Nextstate<=2; end if;
            when 1 =>
                if X='0' then Z<='1'; Nextstate<=3; end if;
                if X='1' then Z<='0'; Nextstate<=4; end if;
            when 2 =>
                if X='0' then Z<='0'; Nextstate<=4; end if;
                if X='1' then Z<='1'; Nextstate<=4; end if;
            when 3 =>
                if X='0' then Z<='0'; Nextstate<=5; end if;
                if X='1' then Z<='1'; Nextstate<=5; end if;
            when 4 =>
                if X='0' then Z<='1'; Nextstate<=5; end if;
                if X='1' then Z<='0'; Nextstate<=6; end if;
            when 5 =>
                if X='0' then Z<='0'; Nextstate<=0; end if;
                if X='1' then Z<='1'; Nextstate<=0; end if;
            when 6 =>
                if X='0' then Z<='1'; Nextstate<=0; end if;
            when others => null; -- should not occur
	end case;   
	wait on CLK, X;
	if (rising_edge(CLK)) then   -- rising_edge function is in BITLIB 
            State <= Nextstate;   
            wait for 0 ns;       -- wait for State to be updated
	end if;
    end process;
end table;