library BITLIB;
use BITLIB.bit_pack.all;

entity ROM1_2 is
  port(X,CLK: in bit;
       Z: out bit);
end ROM1_2;

architecture ROM1 of ROM1_2 is
signal Q, Qplus: bit_vector(1 to 3) := "000";
type ROM is array (0 to 15) of bit_vector(3 downto 0);
constant FSM_ROM:  ROM := 
                ("1001","1010","0000","0000",
                 "0001","0000","0000","0001",
                 "1111","1100","1100","1101",
                 "0111","0100","0110","0111");
begin
  process(Q,X)		-- determines the next state and output
  variable ROMValue: bit_vector(3 downto 0);
  begin
    ROMValue := FSM_ROM(vec2int(Q & X));   -- read ROM output
    Qplus <= ROMValue(3 downto 1);
    Z <= ROMValue(0);
  end process;

  process(CLK)		
  begin
    if CLK='1' then Q <= Qplus; end if;   -- update state register
  end process;
end ROM1;