entity scanner is
  port (R0,R1,R2,R3,CLK: in bit;
	C0,C1,C2: inout bit;
	N0,N1,N2,N3,V: out bit);
end scanner;

architecture scan1 of scanner is
signal Q1,QA, K, Kd: bit;
alias Q2: bit is C0;				-- column outputs will be the same 
alias Q3: bit is C1;				--  as the state variables because
alias Q4: bit is C2;   			--  of state assignment
begin
  K <= R0 or R1 or R2 or R3;			-- this is the decoder section
  N3 <= (R2 and not C0) or (R3 and not C1);
  N2 <= R1 or (R2 and C0);
  N1 <= (R0 and not C0) or (not R2 and C2) or (not R1 and not R0 and C0);
  N0 <= (R1 and C1) or (not R1 and C2) or (not R3 and not R1 and not C1);
  V <= (Q2 and not Q3 and K) or (not Q2 and Q3 and K) or (not Q2 and Q4);
  process(CLK)					-- process to update flip-flops
  begin
    if CLK = '1' then
	Q1 <= (Q1 and Kd) or (Q2 and not Q3 and K) or (not Q2 and Q3 and K) 	  or (not Q2 and Q4);
	Q2 <= (not Q2 and not Q3) or K or Q4;
	Q3 <= not Q3 or Q1 or (Q4 and not Kd) or (not Q2 and K);
	Q4 <= not Q2 or Q1 or (Q3 and not Kd) or (not Q3 and K);
	QA <= K or (QA and not Q1);		-- first debounce flip-flop
	Kd <= QA;					-- second debounce flip-flop
    end if;
  end process;
end scan1;