library BITLIB;
use BITLIB.bit_pack.all;

entity mult2C is
        port (CLK, St: in bit;
              Mplier,Mcand : in bit_vector(3 downto 0);
              Product: out bit_vector (6 downto 0);
              Done: out bit);
end mult2C;

architecture behave1 of mult2C is
  signal State : integer range 0 to 5;
  signal A, B: bit_vector(3 downto 0);
  alias M: bit is B(0);
begin     
  process
  variable addout: bit_vector(4 downto 0); 
  begin
    wait until CLK = '1';
    case State is
        when 0=>					--initial State
          if St='1' then 
            A <= "0000";			--Begin cycle
            B <= Mplier;			--load the multiplier
            State <= 1;
          end if;
        when 1 | 2 | 3  =>			--"add/shift" State
          if M = '1' then
            addout := add4(A,Mcand,'0');	--Add multiplicand to A and shift
            A <= Mcand(3) & addout(3 downto 1); 
            B <= addout(0) & B(3 downto 1);
          else
            A <= A(3) & A(3 downto 1);	--Arithmetic right shift
            B <= A(0) & B(3 downto 1);
          end if;
          State <= State + 1;
        when 4  =>				--add complement if sign bit 
          if M = '1' then			--of multiplier is 1
            addout := add4(A, not Mcand,'1');
            A <= not Mcand(3) & addout(3 downto 1);
            B <= addout(0) & B(3 downto 1);
          else 
            A <= A(3) & A(3 downto 1);	--Arithmetic right shift
            B <= A(0) & B(3 downto 1);
          end if;
          State <= 5;
	    wait for 0 ns;
          Done <= '1';
          Product <= A(2 downto 0) & B;		--output product
        when 5 =>				
          State <= 0;
          Done <= '0';   
    end case;
  end process;
end behave1;