-- Although the VHDL of Figure 4-16 in the text is correct, it will not work
-- with the command file of Figure 4-12 and the test bench of Figure 4-14. 
-- The revised code given below works correctly with these test files. The 
-- revised code is also better because it uses a separate process for the 
-- combinational logic and does all of the register updates in another process.

library BITLIB;
use BITLIB.bit_pack.all;

entity mult2Cs is
        port (CLK, St: in bit;
              Mplier,Mcand : in bit_vector(3 downto 0);
              Product: out bit_vector (6 downto 0);
	      Done: out bit);
end mult2Cs;

-- This architecture of a 4-bit multiplier for 2's complement 
-- numbers uses control signals.
architecture behave2 of mult2Cs is
  signal State, Nextstate: integer range 0 to 5;
  signal A, B: bit_vector(3 downto 0);
  signal AdSh, Sh, Load, Cm: bit;
  signal addout: bit_vector(4 downto 0);
  alias M: bit is B(0);
 
begin     
  process (state, st, M)  
  begin
    Load <= '0'; AdSh <= '0'; Sh <= '0'; Cm <= '0'; Done <= '0'; 
    case State is
        when 0=>					--initial State
          if St='1' then Load <= '1'; Nextstate <= 1; end if;
        when 1 | 2 | 3  =>			--"add/shift" State
          if M = '1' then AdSh <= '1';
            else Sh <= '1';
          end if;
          Nextstate <= State + 1;
        when 4  =>				--add complement if sign 
          if M = '1' then			--bit of multiplier is 1
            Cm <= '1'; AdSh <= '1';
            else Sh <= '1';
          end if;
          nextstate <= 5;
        when 5 =>				--output product
          done <= '1';
          nextstate <= 0;
    end case;
    end process;
    
    addout <= add4(A, Mcand, '0') when Cm = '0'
  			else add4(A, not Mcand, '1');

    process
    begin
    wait until CLK = '1';			--executes on rising edge
    if Load = '1' then				--load the multiplier
        A <= "0000";
        B <= Mplier;
    end if;
    if AdSh = '1' then				--Add multiplicand to A and shift
        A <= (Mcand(3) xor Cm) & addout(3 downto 1);
        B <= addout(0) & B(3 downto 1);
    end if;
    if Sh = '1' then
        A <= A(3) & A(3 downto 1);
        B <= A(0) & B(3 downto 1);
    end if;
    State <= Nextstate;  
    end process;   

    Product <= A(2 downto 0) & B;
  
end behave2;