-- This model of a 4-bit multiplier for 2's complement numbers -- implements the controller using a counter and logic equations. library BITLIB; use BITLIB.bit_pack.all; entity mult2CEQ is port(CLK, St: in bit; Mplier,Mcand: in bit_vector(3 downto 0); Product: out bit_vector(6 downto 0)); end mult2CEQ; architecture m2ceq of mult2CEQ is signal A, B, Q, Comp: bit_vector(3 downto 0); signal addout: bit_vector(4 downto 0); signal AdSh, Sh, Load, Cm, Done, Ld1, CLR1, P1: bit; Signal One: bit:='1'; Signal Din: bit_vector(3 downto 0) := "0100"; alias M: bit is B(0); begin Count1: C74163 port map (Ld1, CLR1, P1, One, CLK, Din, open, Q); P1 <= Q(2); CLR1 <= not Q(3); Done <= Q(3); Sh <= not M and Q(2); AdSh <= M and Q(2); Cm <= Q(1) and Q(0) and M; Load <= not Q(3) and not Q(2) and St; Ld1 <= not Load; Comp <= Mcand xor (Cm & Cm & Cm & Cm); --complement Mcand if Cm='1' addout <= add4(A,Comp,Cm); --add complementer output to A process begin wait until CLK = '1'; --executes on rising edge if Load = '1' then --load the multiplier A <= "0000"; B <= Mplier; end if; if AdSh = '1' then --Add multiplicand to A and shift A <= (Mcand(3) xor Cm) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); end if; if Sh = '1' then --Right shift with sign extend A <= A(3) & A(3 downto 1); B <= A(0) & B(3 downto 1); end if; if Done = '1' then Product <= A(2 downto 0) & B; end if; end process; end m2ceq;