-- Copyright (C) 1991-2004 Altera Corporation -- Any megafunction design, and related netlist (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only -- to program PLD devices (but not masked PLD devices) from Altera. Any -- other use of such megafunction design, netlist, support information, -- device programming or simulation file, or any other related documentation -- or information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to the -- intellectual property, including patents, copyrights, trademarks, trade -- secrets, or maskworks, embodied in any such megafunction design, netlist, -- support information, device programming or simulation file, or any other -- related documentation or information provided by Altera or a megafunction -- partner, remains with Altera, the megafunction partner, or their respective -- licensors. No other licenses, including any licenses needed under any third -- party's intellectual property, are provided herein. -- VENDOR "Altera" -- PROGRAM "Quartus II" -- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version" -- DATE "03/31/2005 09:50:09" -- -- Device: Altera EPF10K30EFC256-1 Package FBGA256 -- -- -- This VHDL file should be used for ModelSim (VHDL output from Quartus II) only -- LIBRARY IEEE, flex10ke; USE IEEE.std_logic_1164.all; USE flex10ke.flex10ke_components.all; ENTITY DiceGame IS PORT ( Rb : IN std_logic; CLK : IN std_logic; Sum : IN std_logic_vector(3 DOWNTO 0); Reset : IN std_logic; Roll : OUT std_logic; Win : OUT std_logic; Lose : OUT std_logic ); END DiceGame; ARCHITECTURE structure OF DiceGame IS SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; SIGNAL devclrn : std_logic := '1'; SIGNAL devpor : std_logic := '1'; SIGNAL devoe : std_logic := '0'; SIGNAL ww_Rb : std_logic; SIGNAL ww_CLK : std_logic; SIGNAL ww_Sum : std_logic_vector(3 DOWNTO 0); SIGNAL ww_Reset : std_logic; SIGNAL ww_Roll : std_logic; SIGNAL ww_Win : std_logic; SIGNAL ww_Lose : std_logic; SIGNAL Point_a2_a : std_logic; SIGNAL reduce_nor_a66 : std_logic; SIGNAL Point_a3_a : std_logic; SIGNAL Sum_a1_a_adataout : std_logic; SIGNAL CLK_adataout : std_logic; SIGNAL Point_a1_a : std_logic; SIGNAL Sum_a3_a_adataout : std_logic; SIGNAL Sum_a0_a_adataout : std_logic; SIGNAL Point_a0_a : std_logic; SIGNAL Sum_a2_a_adataout : std_logic; SIGNAL reduce_nor_a66_cascout : std_logic; SIGNAL reduce_nor_a68 : std_logic; SIGNAL reduce_nor_a63 : std_logic; SIGNAL Nextstate_as4_a352 : std_logic; SIGNAL Rb_adataout : std_logic; SIGNAL Nextstate_as2_a201 : std_logic; SIGNAL Nextstate_a50 : std_logic; SIGNAL Reset_adataout : std_logic; SIGNAL Nextstate_as3_a102 : std_logic; SIGNAL Nextstate_as3_a103 : std_logic; SIGNAL State_a13 : std_logic; SIGNAL Nextstate_as2_a202 : std_logic; SIGNAL State_a12 : std_logic; SIGNAL Nextstate_as0_a14 : std_logic; SIGNAL State_a10 : std_logic; SIGNAL State_a11 : std_logic; SIGNAL process0_a88 : std_logic; SIGNAL Nextstate_as4_a4 : std_logic; SIGNAL State_a14 : std_logic; SIGNAL State_a15 : std_logic; SIGNAL Select_a22 : std_logic; BEGIN ww_Rb <= Rb; ww_CLK <= CLK; ww_Sum <= Sum; ww_Reset <= Reset; Roll <= ww_Roll; Win <= ww_Win; Lose <= ww_Lose; Point_a2_a_aI : flex10ke_lcell -- Equation(s): -- Point_a2_a = DFFEA(Sum_a2_a_adataout, GLOBAL(CLK_adataout), , , Nextstate_as4_a4, , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF00", clock_enable_mode => "true", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Nextstate_as4_a4, datad => Sum_a2_a_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => Point_a2_a); Point_a3_a_aI : flex10ke_lcell -- Equation(s): -- Point_a3_a = DFFEA(Sum_a3_a_adataout, GLOBAL(CLK_adataout), , , Nextstate_as4_a4, , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF00", clock_enable_mode => "true", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Nextstate_as4_a4, datad => Sum_a3_a_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => Point_a3_a); Sum_a1_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(1), dataout => Sum_a1_a_adataout); CLK_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_CLK, dataout => CLK_adataout); Point_a1_a_aI : flex10ke_lcell -- Equation(s): -- Point_a1_a = DFFEA(Sum_a1_a_adataout, GLOBAL(CLK_adataout), , , Nextstate_as4_a4, , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF00", clock_enable_mode => "true", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Nextstate_as4_a4, datad => Sum_a1_a_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => Point_a1_a); Sum_a3_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(3), dataout => Sum_a3_a_adataout); Sum_a0_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(0), dataout => Sum_a0_a_adataout); Point_a0_a_aI : flex10ke_lcell -- Equation(s): -- Point_a0_a = DFFEA(Sum_a0_a_adataout, GLOBAL(CLK_adataout), , , Nextstate_as4_a4, , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF00", clock_enable_mode => "true", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Nextstate_as4_a4, datad => Sum_a0_a_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => Point_a0_a); Sum_a2_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(2), dataout => Sum_a2_a_adataout); reduce_nor_a66_I : flex10ke_lcell -- Equation(s): -- reduce_nor_a66_cascout = Point_a2_a & Sum_a2_a_adataout & (Point_a0_a $ !Sum_a0_a_adataout) # !Point_a2_a & !Sum_a2_a_adataout & (Point_a0_a $ !Sum_a0_a_adataout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "8241", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => Point_a2_a, datab => Point_a0_a, datac => Sum_a0_a_adataout, datad => Sum_a2_a_adataout, devclrn => devclrn, devpor => devpor, cascout => reduce_nor_a66_cascout); reduce_nor_a68_I : flex10ke_lcell -- Equation(s): -- reduce_nor_a68 = (Point_a3_a & Sum_a3_a_adataout & (Point_a1_a $ !Sum_a1_a_adataout) # !Point_a3_a & !Sum_a3_a_adataout & (Point_a1_a $ !Sum_a1_a_adataout)) & CASCADE(reduce_nor_a66_cascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "8241", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Point_a3_a, datab => Point_a1_a, datac => Sum_a1_a_adataout, datad => Sum_a3_a_adataout, cascin => reduce_nor_a66_cascout, devclrn => devclrn, devpor => devpor, combout => reduce_nor_a68); reduce_nor_a63_I : flex10ke_lcell -- Equation(s): -- reduce_nor_a63 = Sum_a3_a_adataout # !Sum_a0_a_adataout # !Sum_a1_a_adataout # !Sum_a2_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF7F", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a2_a_adataout, datab => Sum_a1_a_adataout, datac => Sum_a0_a_adataout, datad => Sum_a3_a_adataout, devclrn => devclrn, devpor => devpor, combout => reduce_nor_a63); Nextstate_as4_a352_I : flex10ke_lcell -- Equation(s): -- Nextstate_as4_a352 = !reduce_nor_a68 & reduce_nor_a63 & State_a15 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "3000", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => reduce_nor_a68, datac => reduce_nor_a63, datad => State_a15, devclrn => devclrn, devpor => devpor, combout => Nextstate_as4_a352); Rb_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Rb, dataout => Rb_adataout); Nextstate_as2_a201_I : flex10ke_lcell -- Equation(s): -- Nextstate_as2_a201 = !Rb_adataout & State_a11 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0F00", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datac => Rb_adataout, datad => State_a11, devclrn => devclrn, devpor => devpor, combout => Nextstate_as2_a201); Nextstate_a50_I : flex10ke_lcell -- Equation(s): -- Nextstate_a50 = Sum_a2_a_adataout $ !Sum_a3_a_adataout # !Sum_a1_a_adataout # !Sum_a0_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "F77F", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a0_a_adataout, datab => Sum_a1_a_adataout, datac => Sum_a2_a_adataout, datad => Sum_a3_a_adataout, devclrn => devclrn, devpor => devpor, combout => Nextstate_a50); Reset_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Reset, dataout => Reset_adataout); Nextstate_as3_a102_I : flex10ke_lcell -- Equation(s): -- Nextstate_as3_a102 = !Rb_adataout & !reduce_nor_a63 & !reduce_nor_a68 & State_a15 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0100", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Rb_adataout, datab => reduce_nor_a63, datac => reduce_nor_a68, datad => State_a15, devclrn => devclrn, devpor => devpor, combout => Nextstate_as3_a102); Nextstate_as3_a103_I : flex10ke_lcell -- Equation(s): -- Nextstate_as3_a103 = Nextstate_as3_a102 # !Reset_adataout & State_a13 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF30", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => Reset_adataout, datac => State_a13, datad => Nextstate_as3_a102, devclrn => devclrn, devpor => devpor, combout => Nextstate_as3_a103); State_a13_I : flex10ke_lcell -- Equation(s): -- State_a13 = DFFEA(Nextstate_as3_a103 # !process0_a88 & Nextstate_as2_a201 & Nextstate_a50, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF40", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => process0_a88, datab => Nextstate_as2_a201, datac => Nextstate_a50, datad => Nextstate_as3_a103, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a13); Nextstate_as2_a202_I : flex10ke_lcell -- Equation(s): -- Nextstate_as2_a202 = Reset_adataout & !Nextstate_a50 & Nextstate_as2_a201 # !Reset_adataout & (State_a12 # !Nextstate_a50 & Nextstate_as2_a201) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "7350", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Reset_adataout, datab => Nextstate_a50, datac => State_a12, datad => Nextstate_as2_a201, devclrn => devclrn, devpor => devpor, combout => Nextstate_as2_a202); State_a12_I : flex10ke_lcell -- Equation(s): -- State_a12 = DFFEA(Nextstate_as2_a202 # !Rb_adataout & State_a15 & reduce_nor_a68, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF40", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Rb_adataout, datab => State_a15, datac => reduce_nor_a68, datad => Nextstate_as2_a202, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a12); Nextstate_as0_a14_I : flex10ke_lcell -- Equation(s): -- Nextstate_as0_a14 = Reset_adataout & (State_a13 # State_a12) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FC00", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => State_a13, datac => State_a12, datad => Reset_adataout, devclrn => devclrn, devpor => devpor, combout => Nextstate_as0_a14); State_a10_I : flex10ke_lcell -- Equation(s): -- State_a10 = DFFEA(!Nextstate_as0_a14 & (State_a10 # Rb_adataout), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "00FC", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => State_a10, datac => Rb_adataout, datad => Nextstate_as0_a14, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a10); State_a11_I : flex10ke_lcell -- Equation(s): -- State_a11 = DFFEA(Rb_adataout & (State_a11 # !State_a10), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "F300", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => State_a10, datac => State_a11, datad => Rb_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a11); process0_a88_I : flex10ke_lcell -- Equation(s): -- process0_a88 = Sum_a1_a_adataout & (Sum_a2_a_adataout # Sum_a3_a_adataout) # !Sum_a1_a_adataout & (Sum_a0_a_adataout # !Sum_a3_a_adataout # !Sum_a2_a_adataout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "EFF5", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a1_a_adataout, datab => Sum_a0_a_adataout, datac => Sum_a2_a_adataout, datad => Sum_a3_a_adataout, devclrn => devclrn, devpor => devpor, combout => process0_a88); Nextstate_as4_a4_I : flex10ke_lcell -- Equation(s): -- Nextstate_as4_a4 = !Rb_adataout & State_a11 & Nextstate_a50 & process0_a88 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "4000", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Rb_adataout, datab => State_a11, datac => Nextstate_a50, datad => process0_a88, devclrn => devclrn, devpor => devpor, combout => Nextstate_as4_a4); State_a14_I : flex10ke_lcell -- Equation(s): -- State_a14 = DFFEA(Nextstate_as4_a4 # !Rb_adataout & (Nextstate_as4_a352 # State_a14), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FF54", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Rb_adataout, datab => Nextstate_as4_a352, datac => State_a14, datad => Nextstate_as4_a4, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a14); State_a15_I : flex10ke_lcell -- Equation(s): -- State_a15 = DFFEA(Rb_adataout & (State_a14 # State_a15), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FC00", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => State_a14, datac => State_a15, datad => Rb_adataout, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => State_a15); Select_a22_I : flex10ke_lcell -- Equation(s): -- Select_a22 = Rb_adataout & (State_a15 # State_a11) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FC00", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => State_a15, datac => State_a11, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, combout => Select_a22); Roll_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => Select_a22, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Roll); Win_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => State_a12, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Win); Lose_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => State_a13, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Lose); END structure;