-- Copyright (C) 1991-2004 Altera Corporation -- Any megafunction design, and related netlist (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only -- to program PLD devices (but not masked PLD devices) from Altera. Any -- other use of such megafunction design, netlist, support information, -- device programming or simulation file, or any other related documentation -- or information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to the -- intellectual property, including patents, copyrights, trademarks, trade -- secrets, or maskworks, embodied in any such megafunction design, netlist, -- support information, device programming or simulation file, or any other -- related documentation or information provided by Altera or a megafunction -- partner, remains with Altera, the megafunction partner, or their respective -- licensors. No other licenses, including any licenses needed under any third -- party's intellectual property, are provided herein. -- VENDOR "Altera" -- PROGRAM "Quartus II" -- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version" -- DATE "03/29/2005 17:07:42" -- -- Device: Altera EPF10K30EFC256-1 Package FBGA256 -- -- -- This VHDL file should be used for ModelSim (VHDL output from Quartus II) only -- LIBRARY IEEE, flex10ke; USE IEEE.std_logic_1164.all; USE flex10ke.flex10ke_components.all; ENTITY dice_game IS PORT ( Rb : IN std_logic; CLK : IN std_logic; Reset : IN std_logic; Sum : IN std_logic_vector(3 DOWNTO 0); Lose : OUT std_logic; Roll : OUT std_logic; Win : OUT std_logic ); END dice_game; ARCHITECTURE structure OF dice_game IS SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; SIGNAL devclrn : std_logic := '1'; SIGNAL devpor : std_logic := '1'; SIGNAL devoe : std_logic := '0'; SIGNAL ww_Rb : std_logic; SIGNAL ww_CLK : std_logic; SIGNAL ww_Reset : std_logic; SIGNAL ww_Sum : std_logic_vector(3 DOWNTO 0); SIGNAL ww_Lose : std_logic; SIGNAL ww_Roll : std_logic; SIGNAL ww_Win : std_logic; SIGNAL ix482 : std_logic; SIGNAL ix466 : std_logic; SIGNAL ix473_a0 : std_logic; SIGNAL ix483 : std_logic; SIGNAL ix476 : std_logic; SIGNAL ix463 : std_logic; SIGNAL modgen_eq_11_ix14 : std_logic; SIGNAL ix478 : std_logic; SIGNAL Reset_adataout : std_logic; SIGNAL Sum_a2_a_adataout : std_logic; SIGNAL Sum_a1_a_adataout : std_logic; SIGNAL Rb_adataout : std_logic; SIGNAL ix467_lc : std_logic; SIGNAL Sum_a0_a_adataout : std_logic; SIGNAL ix469_lc : std_logic; SIGNAL ix483_acascout : std_logic; SIGNAL ix468_lc_a0 : std_logic; SIGNAL CLK_adataout : std_logic; SIGNAL reg_State_1 : std_logic; SIGNAL ix481_lc : std_logic; SIGNAL ix462_lc : std_logic; SIGNAL ix470_lc : std_logic; SIGNAL ix471_lc : std_logic; SIGNAL reg_State_0 : std_logic; SIGNAL Sum_a3_a_adataout : std_logic; SIGNAL ix479_lc : std_logic; SIGNAL ix480_lc : std_logic; SIGNAL ix462_lc_a0 : std_logic; SIGNAL ix461_lc_a0 : std_logic; SIGNAL reg_Point_1 : std_logic; SIGNAL reg_Point_0 : std_logic; SIGNAL reg_Point_3 : std_logic; SIGNAL reg_Point_2 : std_logic; SIGNAL modgen_eq_11_ix14_acascout : std_logic; SIGNAL modgen_eq_11_ix18_lc_a0 : std_logic; SIGNAL ix481_lc_a0 : std_logic; SIGNAL ix472_lc_a0 : std_logic; SIGNAL ix463_acascout : std_logic; SIGNAL ix477_lc_a0 : std_logic; SIGNAL ix482_acascout : std_logic; SIGNAL reg_State_3 : std_logic; SIGNAL ix476_acascout : std_logic; SIGNAL ix465_lc_a0 : std_logic; SIGNAL ix464_lc : std_logic; SIGNAL ix478_acascout : std_logic; SIGNAL ix474_lc_a0 : std_logic; SIGNAL ix475_lc : std_logic; SIGNAL ix466_acascout : std_logic; SIGNAL ix473_a0_cascout : std_logic; SIGNAL reg_State_2 : std_logic; SIGNAL ix503_lc : std_logic; SIGNAL ix501_lc : std_logic; SIGNAL ix502_lc : std_logic; BEGIN ww_Rb <= Rb; ww_CLK <= CLK; ww_Reset <= Reset; ww_Sum <= Sum; Lose <= ww_Lose; Roll <= ww_Roll; Win <= ww_Win; Reset_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Reset, dataout => Reset_adataout); Sum_a2_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(2), dataout => Sum_a2_a_adataout); Sum_a1_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(1), dataout => Sum_a1_a_adataout); Rb_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Rb, dataout => Rb_adataout); ix467 : flex10ke_lcell -- Equation(s): -- ix467_lc = reg_State_1 & !Rb_adataout # !reg_State_1 & Reset_adataout & reg_State_3 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "08F8", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Reset_adataout, datab => reg_State_3, datac => reg_State_1, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, combout => ix467_lc); Sum_a0_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(0), dataout => Sum_a0_a_adataout); ix469 : flex10ke_lcell -- Equation(s): -- ix469_lc = Sum_a3_a_adataout $ !Sum_a2_a_adataout # !Sum_a0_a_adataout # !Sum_a1_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "9FFF", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Sum_a1_a_adataout, datad => Sum_a0_a_adataout, devclrn => devclrn, devpor => devpor, combout => ix469_lc); ix483_aI : flex10ke_lcell -- Equation(s): -- ix483_acascout = !modgen_eq_11_ix18_lc_a0 & !Rb_adataout # !reg_State_3 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "333F", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( datab => reg_State_3, datac => modgen_eq_11_ix18_lc_a0, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, cascout => ix483_acascout); ix468_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix468_lc_a0 = (reg_State_3 # reg_State_1 # !Rb_adataout & ix469_lc) & CASCADE(ix483_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "EFEE", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => reg_State_3, datab => reg_State_1, datac => Rb_adataout, datad => ix469_lc, cascin => ix483_acascout, devclrn => devclrn, devpor => devpor, combout => ix468_lc_a0); CLK_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_CLK, dataout => CLK_adataout); reg_State_1_aI : flex10ke_lcell -- Equation(s): -- reg_State_1 = DFFEA(reg_State_2 & ix467_lc # !reg_State_2 & ix468_lc_a0, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "F3C0", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => reg_State_2, datac => ix467_lc, datad => ix468_lc_a0, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_State_1); ix481 : flex10ke_lcell -- Equation(s): -- ix481_lc = Sum_a1_a_adataout & Sum_a0_a_adataout -- ix481_lc_a0 = Sum_a1_a_adataout & Sum_a0_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "F000", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datac => Sum_a1_a_adataout, datad => Sum_a0_a_adataout, devclrn => devclrn, devpor => devpor, combout => ix481_lc, cascout => ix481_lc_a0); ix462 : flex10ke_lcell -- Equation(s): -- ix462_lc = !Rb_adataout & (Sum_a3_a_adataout $ !Sum_a2_a_adataout # !ix481_lc) -- ix462_lc_a0 = !Rb_adataout & (Sum_a3_a_adataout $ !Sum_a2_a_adataout # !ix481_lc) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "090F", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Rb_adataout, datad => ix481_lc, devclrn => devclrn, devpor => devpor, combout => ix462_lc, cascout => ix462_lc_a0); ix470 : flex10ke_lcell -- Equation(s): -- ix470_lc = reg_State_1 & (Reset_adataout # reg_State_2) # !reg_State_1 & !reg_State_2 & !ix462_lc -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "E0E3", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Reset_adataout, datab => reg_State_2, datac => reg_State_1, datad => ix462_lc, devclrn => devclrn, devpor => devpor, combout => ix470_lc); ix471 : flex10ke_lcell -- Equation(s): -- ix471_lc = reg_State_2 & !reg_State_1 # !reg_State_2 & modgen_eq_11_ix18_lc_a0 & !Rb_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "2272", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => reg_State_2, datab => reg_State_1, datac => modgen_eq_11_ix18_lc_a0, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, combout => ix471_lc); reg_State_0_aI : flex10ke_lcell -- Equation(s): -- reg_State_0 = DFFEA(reg_State_3 & ix471_lc # !reg_State_3 & ix470_lc, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FC30", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => reg_State_3, datac => ix470_lc, datad => ix471_lc, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_State_0); Sum_a3_a_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "input", reg_source_mode => "none", feedback_mode => "from_pin") -- pragma translate_on PORT MAP ( devclrn => devclrn, devpor => devpor, devoe => devoe, oe => GND, ena => VCC, padio => ww_Sum(3), dataout => Sum_a3_a_adataout); ix479 : flex10ke_lcell -- Equation(s): -- ix479_lc = !Sum_a3_a_adataout & (Sum_a2_a_adataout # !Sum_a1_a_adataout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "3033", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => Sum_a3_a_adataout, datac => Sum_a2_a_adataout, datad => Sum_a1_a_adataout, devclrn => devclrn, devpor => devpor, combout => ix479_lc); ix480 : flex10ke_lcell -- Equation(s): -- ix480_lc = Sum_a3_a_adataout & (Sum_a1_a_adataout # Sum_a0_a_adataout # !Sum_a2_a_adataout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "AAA2", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Sum_a1_a_adataout, datad => Sum_a0_a_adataout, devclrn => devclrn, devpor => devpor, combout => ix480_lc); ix461_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix461_lc_a0 = (!reg_State_2 & reg_State_0 & (ix479_lc # ix480_lc)) & CASCADE(ix462_lc_a0) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "4440", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => reg_State_2, datab => reg_State_0, datac => ix479_lc, datad => ix480_lc, cascin => ix462_lc_a0, devclrn => devclrn, devpor => devpor, combout => ix461_lc_a0); reg_Point_1_aI : flex10ke_lcell -- Equation(s): -- reg_Point_1 = DFFEA(Sum_a1_a_adataout & (reg_Point_1 # ix461_lc_a0) # !Sum_a1_a_adataout & reg_Point_1 & !ix461_lc_a0, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "CCF0", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => Sum_a1_a_adataout, datac => reg_Point_1, datad => ix461_lc_a0, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_Point_1); reg_Point_0_aI : flex10ke_lcell -- Equation(s): -- reg_Point_0 = DFFEA(Sum_a0_a_adataout & (reg_Point_0 # ix461_lc_a0) # !Sum_a0_a_adataout & reg_Point_0 & !ix461_lc_a0, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "CCF0", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => Sum_a0_a_adataout, datac => reg_Point_0, datad => ix461_lc_a0, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_Point_0); reg_Point_3_aI : flex10ke_lcell -- Equation(s): -- reg_Point_3 = DFFEA(Sum_a3_a_adataout & (reg_Point_3 # ix461_lc_a0) # !Sum_a3_a_adataout & reg_Point_3 & !ix461_lc_a0, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "CCF0", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => Sum_a3_a_adataout, datac => reg_Point_3, datad => ix461_lc_a0, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_Point_3); reg_Point_2_aI : flex10ke_lcell -- Equation(s): -- reg_Point_2 = DFFEA(Sum_a2_a_adataout & (reg_Point_2 # ix461_lc_a0) # !Sum_a2_a_adataout & reg_Point_2 & !ix461_lc_a0, GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "CCF0", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( datab => Sum_a2_a_adataout, datac => reg_Point_2, datad => ix461_lc_a0, clk => CLK_adataout, devclrn => devclrn, devpor => devpor, regout => reg_Point_2); modgen_eq_11_ix14_aI : flex10ke_lcell -- Equation(s): -- modgen_eq_11_ix14_acascout = Sum_a3_a_adataout & reg_Point_3 & (Sum_a2_a_adataout $ !reg_Point_2) # !Sum_a3_a_adataout & !reg_Point_3 & (Sum_a2_a_adataout $ !reg_Point_2) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "9009", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => reg_Point_3, datac => Sum_a2_a_adataout, datad => reg_Point_2, devclrn => devclrn, devpor => devpor, cascout => modgen_eq_11_ix14_acascout); modgen_eq_11_ix18_lc_a0_I : flex10ke_lcell -- Equation(s): -- modgen_eq_11_ix18_lc_a0 = (Sum_a1_a_adataout & reg_Point_1 & (Sum_a0_a_adataout $ !reg_Point_0) # !Sum_a1_a_adataout & !reg_Point_1 & (Sum_a0_a_adataout $ !reg_Point_0)) & CASCADE(modgen_eq_11_ix14_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "9009", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a1_a_adataout, datab => reg_Point_1, datac => Sum_a0_a_adataout, datad => reg_Point_0, cascin => modgen_eq_11_ix14_acascout, devclrn => devclrn, devpor => devpor, combout => modgen_eq_11_ix18_lc_a0); ix472_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix472_lc_a0 = (!Sum_a3_a_adataout & Sum_a2_a_adataout & !modgen_eq_11_ix18_lc_a0 & !Rb_adataout) & CASCADE(ix481_lc_a0) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0004", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => modgen_eq_11_ix18_lc_a0, datad => Rb_adataout, cascin => ix481_lc_a0, devclrn => devclrn, devpor => devpor, combout => ix472_lc_a0); ix463_aI : flex10ke_lcell -- Equation(s): -- ix463_acascout = Sum_a3_a_adataout & (Sum_a1_a_adataout # Sum_a0_a_adataout # !Sum_a2_a_adataout) # !Sum_a3_a_adataout & (Sum_a2_a_adataout # !Sum_a1_a_adataout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "EFE7", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Sum_a1_a_adataout, datad => Sum_a0_a_adataout, devclrn => devclrn, devpor => devpor, cascout => ix463_acascout); ix477_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix477_lc_a0 = (!reg_State_3 & !reg_State_1 & !Rb_adataout) & CASCADE(ix463_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0003", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datab => reg_State_3, datac => reg_State_1, datad => Rb_adataout, cascin => ix463_acascout, devclrn => devclrn, devpor => devpor, combout => ix477_lc_a0); ix482_aI : flex10ke_lcell -- Equation(s): -- ix482_acascout = reg_State_3 & (reg_State_1 # !Reset_adataout) # !reg_State_2 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "CF4F", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => Reset_adataout, datab => reg_State_3, datac => reg_State_2, datad => reg_State_1, devclrn => devclrn, devpor => devpor, cascout => ix482_acascout); reg_State_3_aI : flex10ke_lcell -- Equation(s): -- reg_State_3 = DFFEA((reg_State_2 # ix477_lc_a0 # reg_State_3 & !ix472_lc_a0) & CASCADE(ix482_acascout), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "FFCE", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => reg_State_3, datab => reg_State_2, datac => ix472_lc_a0, datad => ix477_lc_a0, clk => CLK_adataout, cascin => ix482_acascout, devclrn => devclrn, devpor => devpor, regout => reg_State_3); ix476_aI : flex10ke_lcell -- Equation(s): -- ix476_acascout = !reg_State_2 & !reg_State_1 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "000F", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( datac => reg_State_2, datad => reg_State_1, devclrn => devclrn, devpor => devpor, cascout => ix476_acascout); ix465_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix465_lc_a0 = (!Sum_a3_a_adataout & !Sum_a2_a_adataout & Sum_a1_a_adataout & !reg_State_3) & CASCADE(ix476_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0010", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Sum_a1_a_adataout, datad => reg_State_3, cascin => ix476_acascout, devclrn => devclrn, devpor => devpor, combout => ix465_lc_a0); ix464 : flex10ke_lcell -- Equation(s): -- ix464_lc = Sum_a3_a_adataout & Sum_a2_a_adataout & !Sum_a1_a_adataout & !Sum_a0_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0008", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => Sum_a3_a_adataout, datab => Sum_a2_a_adataout, datac => Sum_a1_a_adataout, datad => Sum_a0_a_adataout, devclrn => devclrn, devpor => devpor, combout => ix464_lc); ix478_aI : flex10ke_lcell -- Equation(s): -- ix478_acascout = !Sum_a3_a_adataout & Sum_a2_a_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0F00", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( datac => Sum_a3_a_adataout, datad => Sum_a2_a_adataout, devclrn => devclrn, devpor => devpor, cascout => ix478_acascout); ix474_lc_a0_I : flex10ke_lcell -- Equation(s): -- ix474_lc_a0 = (reg_State_3 & !reg_State_2 & !modgen_eq_11_ix18_lc_a0 & ix481_lc) & CASCADE(ix478_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0200", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => reg_State_3, datab => reg_State_2, datac => modgen_eq_11_ix18_lc_a0, datad => ix481_lc, cascin => ix478_acascout, devclrn => devclrn, devpor => devpor, combout => ix474_lc_a0); ix475 : flex10ke_lcell -- Equation(s): -- ix475_lc = !reg_State_3 & !reg_State_2 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "000F", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datac => reg_State_3, datad => reg_State_2, devclrn => devclrn, devpor => devpor, combout => ix475_lc); ix466_aI : flex10ke_lcell -- Equation(s): -- ix466_acascout = reg_State_2 & !reg_State_1 # !reg_State_2 & !reg_State_3 & reg_State_1 # !Rb_adataout -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "1CFF", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => reg_State_3, datab => reg_State_2, datac => reg_State_1, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, cascout => ix466_acascout); ix473_a0_I : flex10ke_lcell -- Equation(s): -- ix473_a0_cascout = (!ix474_lc_a0 & (reg_State_1 # !ix475_lc # !ix464_lc)) & CASCADE(ix466_acascout) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0B0F", clock_enable_mode => "false", output_mode => "none") -- pragma translate_on PORT MAP ( dataa => reg_State_1, datab => ix464_lc, datac => ix474_lc_a0, datad => ix475_lc, cascin => ix466_acascout, devclrn => devclrn, devpor => devpor, cascout => ix473_a0_cascout); reg_State_2_aI : flex10ke_lcell -- Equation(s): -- reg_State_2 = DFFEA((!ix465_lc_a0 & (Reset_adataout # reg_State_3 # !ix503_lc)) & CASCADE(ix473_a0_cascout), GLOBAL(CLK_adataout), , , , , ) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0E0F", clock_enable_mode => "false", output_mode => "reg_only") -- pragma translate_on PORT MAP ( dataa => Reset_adataout, datab => reg_State_3, datac => ix465_lc_a0, datad => ix503_lc, clk => CLK_adataout, cascin => ix473_a0_cascout, devclrn => devclrn, devpor => devpor, regout => reg_State_2); ix503 : flex10ke_lcell -- Equation(s): -- ix503_lc = !reg_State_2 & reg_State_1 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "0F00", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datac => reg_State_2, datad => reg_State_1, devclrn => devclrn, devpor => devpor, combout => ix503_lc); ix501 : flex10ke_lcell -- Equation(s): -- ix501_lc = !reg_State_2 & Rb_adataout & (reg_State_3 # !reg_State_1) -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "2300", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( dataa => reg_State_3, datab => reg_State_2, datac => reg_State_1, datad => Rb_adataout, devclrn => devclrn, devpor => devpor, combout => ix501_lc); ix502 : flex10ke_lcell -- Equation(s): -- ix502_lc = reg_State_3 & reg_State_0 -- pragma translate_off GENERIC MAP ( operation_mode => "normal", packed_mode => "false", lut_mask => "F000", clock_enable_mode => "false", output_mode => "comb_only") -- pragma translate_on PORT MAP ( datac => reg_State_3, datad => reg_State_0, devclrn => devclrn, devpor => devpor, combout => ix502_lc); Lose_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => ix503_lc, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Lose); Roll_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => ix501_lc, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Roll); Win_aI : flex10ke_io -- pragma translate_off GENERIC MAP ( operation_mode => "output", reg_source_mode => "none", feedback_mode => "none") -- pragma translate_on PORT MAP ( datain => ix502_lc, devclrn => devclrn, devpor => devpor, devoe => devoe, oe => VCC, ena => VCC, padio => ww_Win); END structure;