-- Behavioral description of the XC4000 CLB

library BITLIB;
use BITLIB.BIT_PACK.ALL;

entity XC4000CLB is
	port (MEM_BITS : in bit_vector(0 to 51);
			G_IN, F_IN, C_IN : in bit_vector(4 downto 1);
			K : in bit;
			Y,X : out bit;
			Q : out bit_vector (1 downto 0));
end XC4000CLB;

architecture behavior of XC4000CLB is

	alias G_FUNC : bit_vector(0 to 15) is MEM_BITS(0 to 15);
	alias F_FUNC : bit_vector(0 to 15) is MEM_BITS(16 to 31);
	alias H_FUNC : bit_vector(0 to 7) is MEM_BITS(32 to 39);
	type bv2D is array (1 downto 0) of bit_vector(1 downto 0);
	constant FF_SEL : bv2D := (MEM_BITS(40 to 41),MEM_BITS(42 to 43));
	alias Y_SEL : bit is MEM_BITS(44);
	alias X_SEL : bit is MEM_BITS(45);
	alias EDGE_SEL: bit_vector(1 downto 0) is MEM_BITS(46 to 47);
	alias EC_SEL : bit_vector(1 downto 0) is MEM_BITS(48 to 49);
	alias SR_SEL : bit_vector(1 downto 0) is MEM_BITS(50 to 51);

	alias H1 : bit is C_IN(1);
	alias DIN : bit is C_IN(2);
	alias SR : bit is C_IN(3);
	alias EC : bit is C_IN(4);

-- Timing spec for XC4000, Speed Grade -4
	constant Tiho : TIME := 6 ns;	-- F/G inputs to X/Y outputs via H
	constant Tilo : TIME := 4 ns;	-- F/G inputs to X/Y outputs
	constant Tcko : TIME := 3 ns;	-- Clock K to Q outputs
	constant Trio : TIME := 7 ns;	-- S/R to Q outputs

	signal G,F,H : bit;

begin
	
	G <= G_FUNC (vec2int(G_IN));
	F <= F_FUNC (vec2int(F_IN));
	H <= H_FUNC (vec2int(H1&G&F)) after (Tiho-Tilo);
	X <= (X_SEL and H) or (not X_SEL and F) after Tilo;
	Y <= (Y_SEL and H) or (not Y_SEL and G) after Tilo;

	process (K, SR)				-- update FF outputs
	variable DFF_EC,D : bit_vector(1 downto 0);
	begin
		for i in 0 to 1 loop
			DFF_EC(i) := EC or EC_SEL(i);
			case FF_SEL(i) is
				when "00" => D(i) := DIN;
				when "01" => D(i) := F;
				when "10" => D(i) := G;
				when "11" => D(i) := H;
			end case;
			if (SR='1') then  -- If SR set, then set or reset ff
				Q(i)<=SR_SEL(i) after Trio;
			else
				if (DFF_EC(i)='1') then  -- If clock enabled then
					-- If correct triggering edge then update ff value
					if ((EDGE_SEL(i)='1' and rising_edge(K)) or (EDGE_SEL(i)='0' 							and falling_edge(K))) then
						Q(i)<=D(i) after Tcko;
					end if; 
				end if;
			end if;
		end loop;
	end process;
end behavior;