-- Fig8_14 (EPF10K10LC84-3)
--
-- Copyright (C) 1988-1998 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- MAX+plus II Version 9.1 RC3 10/28/1998
-- Tue Mar 16 11:42:32 2004

--

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

LIBRARY alt_vtl;
USE alt_vtl.VCOMPONENTS.all;

ENTITY Fig8_14 IS
    PORT (
      a : IN std_logic_vector(1 downto 0);
      b : OUT std_logic);
END Fig8_14;

ARCHITECTURE EPF10K10LC84_a3 OF Fig8_14 IS

SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL
    n_8, n_9, n_10, n_11, n_12, a_a41_aOUT, n_14, n_15, n_16, n_17, n_18,
          n_20, n_21, n_23, n_24 : std_logic;

BEGIN
gnd <= '0';
vcc <= '1';
TRIBUF_2: TRIBUF
    PORT MAP (IN1 => n_8, OE => vcc, Y => b);
delay_3: DELAY
    PORT MAP ( Y => n_8, IN1 => n_9);
XOR2_4: XOR2
    PORT MAP ( Y => n_9, IN1 => n_10, IN2 => n_14);
OR1_5: OR1
    PORT MAP ( Y => n_10, IN1 => n_11);
AND1_6: AND1
    PORT MAP ( Y => n_11, IN1 => n_12);
delay_7: DELAY
    PORT MAP ( Y => n_12, IN1 => a_a41_aOUT);
AND1_8: AND1
    PORT MAP ( Y => n_14, IN1 => gnd);
delay_9: DELAY
    PORT MAP ( Y => a_a41_aOUT, IN1 => n_15);
XOR2_10: XOR2
    PORT MAP ( Y => n_15, IN1 => n_16, IN2 => n_24);
OR2_11: OR2
    PORT MAP ( Y => n_16, IN1 => n_17, IN2 => n_20);
AND1_12: AND1
    PORT MAP ( Y => n_17, IN1 => n_18);
inv_13: INV 
    PORT MAP ( Y => n_18, IN1 => a(0));
AND2_14: AND2
    PORT MAP ( Y => n_20, IN1 => n_21, IN2 => n_23);
delay_15: DELAY
    PORT MAP ( Y => n_21, IN1 => a(1));
delay_16: DELAY
    PORT MAP ( Y => n_23, IN1 => a_a41_aOUT);
AND1_17: AND1
    PORT MAP ( Y => n_24, IN1 => gnd);

END EPF10K10LC84_a3;