library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;

package NEED_IT_TO_COMPILE is
  function ROTATE_LEFT(VECTOR : in std_logic_vector;
                       N : in integer) return std_logic_vector;
end package;

package body NEED_IT_TO_COMPILE is
  function ROTATE_LEFT(VECTOR : in std_logic_vector;
                       N : in integer) return std_logic_vector is
    --variable NEW_VECTOR : std_logic_vector(VECTOR'range);
    alias TEMP_NEW : std_logic_vector(VECTOR'length-1 downto 0) is VECTOR;
    variable TEMP_BIT : std_logic;
  begin
    --TEMP_NEW := VECTOR;
    if (N > VECTOR'length) then
      report "N is greater than the vector length"
      severity warning;
    else
      for I in 0 to N-1 loop
        TEMP_BIT := TEMP_NEW(TEMP_NEW'length-1);
        for J in VECTOR'length-1 downto 1 loop
          TEMP_NEW(J) := TEMP_NEW(J-1);
        end loop;
        TEMP_NEW(0) := TEMP_BIT;
      end loop;
    end if;
    return TEMP_NEW;
  end ROTATE_LEFT;
end package body;

entity test_rotate is
end test_rotate;

library ieee;
use ieee.std_logic_1164.all;
use work.need_it_to_compile.all;

architecture test_orig of test_rotate is
  signal a : std_logic_vector(45 to 59) := "100X-LLWWUZ1011";
  signal b : std_logic_vector(63 downto 56) := "11111101";
  signal c, h, k : std_logic_vector(0 to 14);
  signal d : std_logic_vector(7 downto 0);
begin
  process
    variable e : integer := 5;
    variable f : integer := 0;
    variable g : integer := 10;
  begin
    c <= rotate_left(a, g);
    d <= rotate_left(b, f);
    h <= rotate_left(a, e);
    k <= rotate_left(a, 50);
    wait;
  end process;
end test_orig;