library ieee;
use ieee.std_logic_1164.all;

package NEED_IT is
  function "=" (l, r : in std_logic_vector) return BOOLEAN;
end NEED_IT;

library ieee;
use ieee.std_logic_1164.all;

package body NEED_IT is
  function "=" (l, r : in std_logic_vector) return BOOLEAN is
    alias L_NEW : std_logic_vector(L'length - 1 downto 0) is L;
    alias R_NEW : std_logic_vector(R'length - 1 downto 0) is R;
    variable MATCH : BOOLEAN;
  begin
    assert (L'length = R'length)
    report "Vectors are not the same length"
    severity ERROR;
    MATCH := TRUE;
    for I in L_NEW'range loop
      if ((L_NEW(I) /= '0' and L_NEW(I) /= '1' and L_NEW(I) /= '-') or 
          (R_NEW(I) /= '0' and R_NEW(I) /= '1' and R_NEW(I) /= '-')) then
             report "Vectors have illegal values"
             severity ERROR;
      end if;
      if (L_NEW(I) = '0') then
        if (R_NEW(I) /= '0' and R_NEW(I) /= '-') then
          MATCH := FALSE;
        end if;
      elsif (L_NEW(I) = '1') then
        if (R_NEW(I) /= '1' and R_NEW(I) /= '-') then
          MATCH := FALSE;
        end if;
      end if;
    end loop;
    return MATCH;
  end;
end NEED_IT;

library ieee;
use ieee.std_logic_1164.all;

entity TEST_EQUAL is
end TEST_EQUAL;

use work.NEED_IT.all;
architecture TEST_EQUAL of TEST_EQUAL is
  signal EQUAL : BOOLEAN;
begin
  process
    variable A  : std_logic_vector(8 downto 3) := "0-1011";
    variable B : std_logic_vector (93 downto 86) := "00000000";
    variable C : std_logic_vector(47 to 52) := "011--1";
    variable D : std_logic_vector(0 to 5) := "011-10";
  begin
    EQUAL <= A = B after 10 ns;
    EQUAL <= transport A = C after 20 ns;
    EQUAL <= transport A = D after 30 ns;
    wait;
  end process;
end TEST_EQUAL;

architecture TEST_EQUAL_BRAD of TEST_EQUAL is
  signal EQUAL : BOOLEAN;
begin
  process
    variable A : std_logic_vector(8 downto 3) := "0-1011";
    variable B : std_logic_vector(47 to 52) := "011011";
  begin
    EQUAL <= A = B after 10 ns;
    wait;
  end process;
end TEST_EQUAL_BRAD;