interface tape_if(input bit clk);
  logic RESET, PL, RE, FF, ST, M, P, F, R;
  logic [15:0] COUNT;

  clocking cb @(negedge clk);
    output RESET, PL, RE, FF, ST, M;
    input P, F, R;
  endclocking

  modport TEST (clocking cb);
endinterface

module top;
  bit clk;
  logic ff_one, re_one;
  always #5 clk = ~clk;
  
  tape_if tapeif(clk);
  tape_player u1 (.CLK (clk),
           .RESET (tapeif.RESET),
           .PL (tapeif.PL),
           .RE (re_one),
           .FF (ff_one),
           .ST (tapeif.ST),
           .M (tapeif.M),
           .COUNT (tapeif.COUNT),
           .P (tapeif.P),
           .F (tapeif.F),
           .R (tapeif.R));
  one_cycle u2 (.PUSH (tapeif.FF),
                .CLK (clk),
                .R (tapeif.RESET),
                .SINGLE (ff_one));
  one_cycle u3 (.PUSH (tapeif.RE),
                .CLK (clk),
                .R (tapeif.RESET),
                .SINGLE (re_one));
  test t1(tapeif);
endmodule : top

package mine;
  class Packet;
    // The random variables
    rand int music;
    // Limit the values for music
    constraint music_dist
    { music dist {[20:25] := 10,
                  [26:39] := 20,
                  [40:50] := 15};
    }
  endclass : Packet
endpackage : mine

import mine::*;
module test(tape_if.TEST tapeif);
  Packet p;
  integer in, status;
  logic reset, ff, re, pl, st;
  initial begin
    p = new();
  end
  initial begin
    repeat (10) @ (tapeif.cb);
    repeat (200)
    begin
      while (!$feof(in))
      begin
        status = $fscanf(in, "%b %b %b %b %b\n", 
                         reset, pl, ff, re, st);
        tapeif.cb.RESET <= reset;
        tapeif.cb.FF <= ff;
        tapeif.cb.RE <= re;
        tapeif.cb.PL <= pl;
        tapeif.cb.ST <= st;
        p.randomize();
        if (tapeif.cb.F == 1'b1 || tapeif.cb.R == 1'b1)
        begin
          tapeif.cb.M <= 1'b1;
          repeat (p.music) @tapeif.cb;
          tapeif.cb.M <= 1'b0;
        @(tapeif.cb);
        end
      end // end while
      $rewind(in);
    end // repeat 200
    $finish;
  end // initial
endmodule : test