interface arbiter_if(input bit clk);
  logic [3:0] REQUEST, GRANT, GEN_REQ;
  logic RESET;
  int REQ_TIME3, REQ_TIME2, REQ_TIME1, REQ_TIME0;
endinterface

package mine;
  class Packet_g;
    // The random variables
    rand int generate_t, request_t;
    // Limit the values
    constraint c1 {generate_t < 300; generate_t > 100;
                  request_t < 101; request_t > 0;}  
  endclass : Packet_g
endpackage : mine

/*entity REQ_DEV is
  port(GEN_REQ : in std_logic;
       REQ_TIME : in integer range 0 to 100;
       REQUEST : out std_logic;
       GRANT : in std_logic;
       RESET, CLK : in std_logic);
end REQ_DEV;*/


import mine::*;
module test0(arbiter_if arbif);
  Packet_g p;
  initial begin
    p = new();
    repeat(100)
    begin
      p.randomize();
      repeat(p.generate_t) @(negedge arbif.clk); 
      //wait random nunber of cycles to set reset to 1 (1)
      arbif.RESET <= 1'b1;         //set reset to 1 (1)
      arbif.REQ_TIME1 <= p.request_t; // set random number of cycles to hold high (2)
      @(negedge arbif.clk);		//wait one clock cycle (3)
      arbif.RESET <= 1'b0;		//set the reset to 0 (3)
      @(negedge arbif.clk);		//wait one more clock cycle (4)
      @(negedge arbif.REQUEST[1]);	//wait for re_dev to lower request to 0 (5)
      @(negedge arbif.clk);		//wait one more clock cycle (6)
    end
  end
endmodule : test0