# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, the Altera Quartus Prime License Agreement, # the Altera MegaCore Function License Agreement, or other # applicable license agreement, including, without limitation, # that your use is for the sole purpose of programming logic # devices manufactured by Altera and sold by Altera or its # authorized distributors. Please refer to the applicable # agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition # Date created = 08:57:04 February 18, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # counter_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV GX" set_global_assignment -name DEVICE AUTO set_global_assignment -name TOP_LEVEL_ENTITY counter set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:57:04 FEBRUARY 18, 2020" set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VHDL_FILE prims.vhd set_global_assignment -name VHDL_FILE counter.vhd set_global_assignment -name SOURCE_FILE db/counter.cmp.rdb set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top