-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera MegaCore Function License Agreement, or other 
-- applicable license agreement, including, without limitation, 
-- that your use is for the sole purpose of programming logic 
-- devices manufactured by Altera and sold by Altera or its 
-- authorized distributors.  Please refer to the applicable 
-- agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"

-- DATE "02/18/2020 09:00:17"

-- 
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	COUNTER IS
    PORT (
	RESET : IN std_logic;
	LOAD : IN std_logic;
	COUNT : IN std_logic;
	UP : IN std_logic;
	CLK : IN std_logic;
	DATA_IN : IN STD.STANDARD.bit_vector(3 DOWNTO 0);
	CNT : INOUT std_logic_vector(3 DOWNTO 0)
	);
END COUNTER;

-- Design Ports Information
-- CNT[0]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CNT[1]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CNT[2]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CNT[3]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- COUNT	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- RESET	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- LOAD	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- DATA_IN[0]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CLK	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- UP	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- DATA_IN[1]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- DATA_IN[2]	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- DATA_IN[3]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF COUNTER IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_RESET : std_logic;
SIGNAL ww_LOAD : std_logic;
SIGNAL ww_COUNT : std_logic;
SIGNAL ww_UP : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_DATA_IN : std_logic_vector(3 DOWNTO 0);
SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \CNT[0]~input_o\ : std_logic;
SIGNAL \CNT[1]~input_o\ : std_logic;
SIGNAL \CNT[2]~input_o\ : std_logic;
SIGNAL \CNT[3]~input_o\ : std_logic;
SIGNAL \CNT[0]~output_o\ : std_logic;
SIGNAL \CNT[1]~output_o\ : std_logic;
SIGNAL \CNT[2]~output_o\ : std_logic;
SIGNAL \CNT[3]~output_o\ : std_logic;
SIGNAL \CLK~input_o\ : std_logic;
SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
SIGNAL \LOAD~input_o\ : std_logic;
SIGNAL \DATA_IN[0]~input_o\ : std_logic;
SIGNAL \RESET~input_o\ : std_logic;
SIGNAL \COUNT~input_o\ : std_logic;
SIGNAL \CNT~11_combout\ : std_logic;
SIGNAL \CNT~12_combout\ : std_logic;
SIGNAL \CNT[0]~reg0_q\ : std_logic;
SIGNAL \UP~input_o\ : std_logic;
SIGNAL \CNT~13_combout\ : std_logic;
SIGNAL \CNT[1]~0_combout\ : std_logic;
SIGNAL \DATA_IN[1]~input_o\ : std_logic;
SIGNAL \CNT[1]~reg0_q\ : std_logic;
SIGNAL \CNT~14_combout\ : std_logic;
SIGNAL \CNT[2]~1_combout\ : std_logic;
SIGNAL \DATA_IN[2]~input_o\ : std_logic;
SIGNAL \CNT[2]~reg0_q\ : std_logic;
SIGNAL \CNT[3]~15_combout\ : std_logic;
SIGNAL \CNT[3]~2_combout\ : std_logic;
SIGNAL \DATA_IN[3]~input_o\ : std_logic;
SIGNAL \CNT[3]~reg0_q\ : std_logic;

BEGIN

ww_RESET <= RESET;
ww_LOAD <= LOAD;
ww_COUNT <= COUNT;
ww_UP <= UP;
ww_CLK <= CLK;
ww_DATA_IN <= IEEE.STD_LOGIC_1164.TO_STDLOGICVECTOR(DATA_IN);
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);

-- Location: IOOBUF_X8_Y0_N2
\CNT[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \CNT[0]~reg0_q\,
	oe => VCC,
	devoe => ww_devoe,
	o => \CNT[0]~output_o\);

-- Location: IOOBUF_X12_Y0_N9
\CNT[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \CNT[1]~reg0_q\,
	oe => VCC,
	devoe => ww_devoe,
	o => \CNT[1]~output_o\);

-- Location: IOOBUF_X12_Y0_N2
\CNT[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \CNT[2]~reg0_q\,
	oe => VCC,
	devoe => ww_devoe,
	o => \CNT[2]~output_o\);

-- Location: IOOBUF_X10_Y0_N9
\CNT[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \CNT[3]~reg0_q\,
	oe => VCC,
	devoe => ww_devoe,
	o => \CNT[3]~output_o\);

-- Location: IOIBUF_X16_Y0_N15
\CLK~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_CLK,
	o => \CLK~input_o\);

-- Location: CLKCTRL_G17
\CLK~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \CLK~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \CLK~inputclkctrl_outclk\);

-- Location: IOIBUF_X14_Y0_N1
\LOAD~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_LOAD,
	o => \LOAD~input_o\);

-- Location: IOIBUF_X20_Y0_N8
\DATA_IN[0]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_DATA_IN(0),
	o => \DATA_IN[0]~input_o\);

-- Location: IOIBUF_X22_Y0_N1
\RESET~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_RESET,
	o => \RESET~input_o\);

-- Location: IOIBUF_X24_Y0_N8
\COUNT~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_COUNT,
	o => \COUNT~input_o\);

-- Location: LCCOMB_X17_Y1_N20
\CNT~11\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT~11_combout\ = (!\RESET~input_o\ & (!\LOAD~input_o\ & (\COUNT~input_o\ $ (\CNT[0]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RESET~input_o\,
	datab => \COUNT~input_o\,
	datac => \LOAD~input_o\,
	datad => \CNT[0]~reg0_q\,
	combout => \CNT~11_combout\);

-- Location: LCCOMB_X17_Y1_N18
\CNT~12\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT~12_combout\ = (\CNT~11_combout\) # ((\LOAD~input_o\ & (\DATA_IN[0]~input_o\ & !\RESET~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \LOAD~input_o\,
	datab => \DATA_IN[0]~input_o\,
	datac => \RESET~input_o\,
	datad => \CNT~11_combout\,
	combout => \CNT~12_combout\);

-- Location: FF_X17_Y1_N19
\CNT[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \CNT~12_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \CNT[0]~reg0_q\);

-- Location: IOIBUF_X20_Y0_N1
\UP~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_UP,
	o => \UP~input_o\);

-- Location: LCCOMB_X17_Y1_N2
\CNT~13\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT~13_combout\ = \UP~input_o\ $ (\CNT[1]~reg0_q\ $ (!\CNT[0]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \UP~input_o\,
	datac => \CNT[1]~reg0_q\,
	datad => \CNT[0]~reg0_q\,
	combout => \CNT~13_combout\);

-- Location: LCCOMB_X17_Y1_N8
\CNT[1]~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT[1]~0_combout\ = (\COUNT~input_o\ & ((\CNT~13_combout\))) # (!\COUNT~input_o\ & (\CNT[1]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \COUNT~input_o\,
	datac => \CNT[1]~reg0_q\,
	datad => \CNT~13_combout\,
	combout => \CNT[1]~0_combout\);

-- Location: IOIBUF_X22_Y0_N8
\DATA_IN[1]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_DATA_IN(1),
	o => \DATA_IN[1]~input_o\);

-- Location: FF_X17_Y1_N9
\CNT[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \CNT[1]~0_combout\,
	asdata => \DATA_IN[1]~input_o\,
	sclr => \RESET~input_o\,
	sload => \LOAD~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \CNT[1]~reg0_q\);

-- Location: LCCOMB_X17_Y1_N16
\CNT~14\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT~14_combout\ = \CNT[2]~reg0_q\ $ (((\UP~input_o\ & ((!\CNT[1]~reg0_q\) # (!\CNT[0]~reg0_q\))) # (!\UP~input_o\ & ((\CNT[0]~reg0_q\) # (\CNT[1]~reg0_q\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000101111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \UP~input_o\,
	datab => \CNT[0]~reg0_q\,
	datac => \CNT[1]~reg0_q\,
	datad => \CNT[2]~reg0_q\,
	combout => \CNT~14_combout\);

-- Location: LCCOMB_X17_Y1_N10
\CNT[2]~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT[2]~1_combout\ = (\COUNT~input_o\ & ((!\CNT~14_combout\))) # (!\COUNT~input_o\ & (\CNT[2]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \COUNT~input_o\,
	datac => \CNT[2]~reg0_q\,
	datad => \CNT~14_combout\,
	combout => \CNT[2]~1_combout\);

-- Location: IOIBUF_X24_Y0_N1
\DATA_IN[2]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_DATA_IN(2),
	o => \DATA_IN[2]~input_o\);

-- Location: FF_X17_Y1_N11
\CNT[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \CNT[2]~1_combout\,
	asdata => \DATA_IN[2]~input_o\,
	sclr => \RESET~input_o\,
	sload => \LOAD~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \CNT[2]~reg0_q\);

-- Location: LCCOMB_X17_Y1_N6
\CNT[3]~15\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT[3]~15_combout\ = (\UP~input_o\ & (((!\CNT[2]~reg0_q\) # (!\CNT[1]~reg0_q\)) # (!\CNT[0]~reg0_q\))) # (!\UP~input_o\ & ((\CNT[0]~reg0_q\) # ((\CNT[1]~reg0_q\) # (\CNT[2]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \UP~input_o\,
	datab => \CNT[0]~reg0_q\,
	datac => \CNT[1]~reg0_q\,
	datad => \CNT[2]~reg0_q\,
	combout => \CNT[3]~15_combout\);

-- Location: LCCOMB_X17_Y1_N28
\CNT[3]~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \CNT[3]~2_combout\ = \CNT[3]~reg0_q\ $ (((\COUNT~input_o\ & !\CNT[3]~15_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \COUNT~input_o\,
	datac => \CNT[3]~reg0_q\,
	datad => \CNT[3]~15_combout\,
	combout => \CNT[3]~2_combout\);

-- Location: IOIBUF_X14_Y0_N8
\DATA_IN[3]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_DATA_IN(3),
	o => \DATA_IN[3]~input_o\);

-- Location: FF_X17_Y1_N29
\CNT[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \CNT[3]~2_combout\,
	asdata => \DATA_IN[3]~input_o\,
	sclr => \RESET~input_o\,
	sload => \LOAD~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \CNT[3]~reg0_q\);

-- Location: IOIBUF_X8_Y0_N1
\CNT[0]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => CNT(0),
	o => \CNT[0]~input_o\);

-- Location: IOIBUF_X12_Y0_N8
\CNT[1]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => CNT(1),
	o => \CNT[1]~input_o\);

-- Location: IOIBUF_X12_Y0_N1
\CNT[2]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => CNT(2),
	o => \CNT[2]~input_o\);

-- Location: IOIBUF_X10_Y0_N8
\CNT[3]~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => CNT(3),
	o => \CNT[3]~input_o\);

CNT(0) <= \CNT[0]~output_o\;

CNT(1) <= \CNT[1]~output_o\;

CNT(2) <= \CNT[2]~output_o\;

CNT(3) <= \CNT[3]~output_o\;
END structure;