# //  Questa Sim-64
# //  Version 2020.1 linux_x86_64 Jan 28 2020
# //
# //  Copyright 1991-2020 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading project counter
# Compile of counter.vho was successful.
# Compile of counter_tb.vhd failed with 9 errors.
# Compile of counter_tb.vhd failed with 7 errors.
# Compile of counter_tb.vhd failed with 2 errors.
# Compile of pulse_gen.vhd was successful.
# Compile of counter_tb.vhd failed with 2 errors.
# Compile of counter_tb.vhd failed with 1 errors.
# Compile of pulse_gen.vhd failed with 1 errors.
# Compile of pulse_gen.vhd was successful.
# Compile of counter_tb.vhd was successful.
vsim work.test_bench -vital2.2b -sdftyp /L1=/home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo
# vsim work.test_bench -vital2.2b -sdftyp "/L1=/home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo" 
# Start time: 09:07:35 on Feb 18,2020
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading cycloneiv.cycloneiv_atom_pack(body)
# Loading cycloneiv.cycloneiv_components
# Loading work.test_bench(counter_test)#1
# Loading work.counter(structure)#1
# Loading ieee.std_logic_arith(body)
# Loading cycloneiv.cycloneiv_io_obuf(arch)#2
# Loading cycloneiv.cycloneiv_io_ibuf(arch)#1
# Loading cycloneiv.cycloneiv_clkctrl(vital_clkctrl)#1
# Loading cycloneiv.cycloneiv_ena_reg(behave)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#2
# Loading altera.dffeas(vital_dffeas)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#3
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#4
# Loading altera.dffeas(vital_dffeas)#3
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#5
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#6
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#7
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#8
# Loading work.pulse_gen(alg)#1
# Loading instances from /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo
# Loading timing data from /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(177): Instance '/test_bench/L1/\CNT[0]~reg0\' does not have a generic named 'thold_clk_d_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(239): Instance '/test_bench/L1/\CNT[1]~reg0\' does not have a generic named 'thold_clk_d_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(240): Instance '/test_bench/L1/\CNT[1]~reg0\' does not have a generic named 'thold_clk_sclr_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(241): Instance '/test_bench/L1/\CNT[1]~reg0\' does not have a generic named 'thold_clk_sload_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(242): Instance '/test_bench/L1/\CNT[1]~reg0\' does not have a generic named 'thold_clk_asdata_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(297): Instance '/test_bench/L1/\CNT[2]~reg0\' does not have a generic named 'thold_clk_d_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(298): Instance '/test_bench/L1/\CNT[2]~reg0\' does not have a generic named 'thold_clk_sclr_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(299): Instance '/test_bench/L1/\CNT[2]~reg0\' does not have a generic named 'thold_clk_sload_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(300): Instance '/test_bench/L1/\CNT[2]~reg0\' does not have a generic named 'thold_clk_asdata_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(355): Instance '/test_bench/L1/\CNT[3]~reg0\' does not have a generic named 'thold_clk_d_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(356): Instance '/test_bench/L1/\CNT[3]~reg0\' does not have a generic named 'thold_clk_sclr_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(357): Instance '/test_bench/L1/\CNT[3]~reg0\' does not have a generic named 'thold_clk_sload_posedge'.
# ** Error (suppressible): (vsim-SDF-3240) /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo(358): Instance '/test_bench/L1/\CNT[3]~reg0\' does not have a generic named 'thold_clk_asdata_posedge'.
# Error loading design
# End time: 09:07:36 on Feb 18,2020, Elapsed time: 0:00:01
# Errors: 13, Warnings: 15
vsim -sdftyp /L1=/home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo work.test_bench -t ps
# vsim -sdftyp "/L1=/home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo" work.test_bench -t ps 
# Start time: 09:08:22 on Feb 18,2020
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading cycloneiv.cycloneiv_atom_pack(body)
# Loading cycloneiv.cycloneiv_components
# Loading work.test_bench(counter_test)#1
# Loading work.counter(structure)#1
# Loading ieee.std_logic_arith(body)
# Loading cycloneiv.cycloneiv_io_obuf(arch)#2
# Loading cycloneiv.cycloneiv_io_ibuf(arch)#1
# Loading cycloneiv.cycloneiv_clkctrl(vital_clkctrl)#1
# Loading cycloneiv.cycloneiv_ena_reg(behave)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#2
# Loading altera.dffeas(vital_dffeas)#1
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#3
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#4
# Loading altera.dffeas(vital_dffeas)#3
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#5
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#6
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#7
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)#8
# Loading work.pulse_gen(alg)#1
# Loading instances from /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo
# Loading timing data from /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/simulation/modelsim/counter_vhd.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /test_bench File: /home/facstaff/gaede/public_html/cpe526/logic_primitives/counter/counter_tb.vhd
add wave  \
sim:/test_bench/L1/RESET \
sim:/test_bench/L1/LOAD \
sim:/test_bench/L1/COUNT \
sim:/test_bench/L1/UP \
sim:/test_bench/L1/CLK \
sim:/test_bench/L1/DATA_IN \
sim:/test_bench/L1/CNT
run 1000 ns
run 1000 ns
run 1000 ns
quit
# End time: 09:11:10 on Feb 18,2020, Elapsed time: 0:02:48
# Errors: 0, Warnings: 1