CPE/EE 427, CPE 527 VLSI Design I, Fall 2007



Course Info
Lecture Notes
Labs
Homeworks
Documents
Links

Course Information

Term and Course Credit: Fall 2007, 3 credit hours

Time and Place:  Lecture: MW 3:55 PM - 5:15 PM, Room 239

Instructor: Dr. Aleksandar Milenkovic     
    Email: milenka at ece---uah....edu
    Office: 217-L
    Phone: (256) 824 6830
    Office Hours: M: 1:00-2:00 PM and W: 1:00-2:00 PM

Lab Instructor(s): Joel Wilder
    Email: wilderj at ece.....uah.edu
    Office:  EB 242-C
    Phone:  (256) 824 3484
    Office Hours:  TR 2:00 - 3:00 PM

Class Web page: http://www.ece.uah.edu/~milenka/cpe527-07F

Description
The course gives an introduction to digital integrated circuits.
It covers the following topics. CMOS devices and manufacturing technology. CMOS inverters and gates.
Propagation delay, noise margins, and power dissipation. Sequential circuits, arithmetic, interconnect, and memories. Design methodologies.
A major part of the course will be a design project.

Text Book
Neil H.E. Weste, David Harris,
CMOS VLSI Design: A Circuits and System Perspective, Addison Wesley, 3e,  2005, ISBN: 0-321-14901-7.
 
References
J. Rabaey, A. Chandarakasan, B. Nikolic,
Digital Integrated Circuits: A Design Perspective
Prentice Hall, 2/e, ISBN 0-13-090996-3.
Book Web site: http://bwrc.eecs.berkeley.edu/IcBook/

Prerequisites: EE 202 Introduction to Digital Logic Design, EE 315 Introduction to Electronic Analysis and Design

Academic Misconduct
Academic Honesty.  Your written assignments and examinations must be your own work.  Academic Misconduct will not be tolerated.  To insure that you are aware of what is considered academic misconduct, you should review carefully the definition and examples provided in Article III. Code of Student Conduct, Student Handbook, p. 93. If you have questions in this regard, please contact me without delay.

Use of Prior Work.  You may not submit in fulfillment of requirements in this course any work submitted, presented, or used by you in any other course.

Consent to Use of Turnitin.com.  UAH is committed to the fundamental values of preserving academic honesty as defined in the Student Handbook (7.III.A, Code of Student Conduct).  The instructor reserves the right to utilize electronic means to help prevent plagiarism.  Students agree that by taking this course all assignments are subject to submission for textual similarity review to Turnitin.com.  Assignments submitted to Turnitin.com will be included as source documents in Turnitin.com’s restricted access database solely for the purpose of detecting plagiarism in such documents.  The terms that apply to the University’s use of the Turnitin.com service, as well as additional information about the company, are described at www. uah.edu/library/turnitin.

Classroom Conduct.  All students in the class must treat others with civility and respect and conduct themselves during class sessions in a way that does not unreasonably interfere with the opportunity of other students to learn. Failure to comply with this requirement may result in points being deducted from a student’s final numerical average, up to a maximum of 15 points.

Copyright Aleksandar Milenkovic 2007.  All federal and state copyrights in my lectures and course materials are reserved by me.  You are authorized to take notes in class for your own personal use and for no other purpose. You are not authorized to record my lectures or to make any commercial use of them or to provide them to anyone else other than students currently enrolled in this course, without my prior written permission.  In addition to legal sanctions for violations of copyright law, students found in violation of these prohibitions may be subject to University disciplinary action under the Code of student Conduct.

Exam Dates
Test I - October 11, 2007
Test II – November 26, 2007
Final Project due – December 5 (Wednesday), 2007 (3:00PM)

Grading Policy
Final course grades will be determined in the manner outlined below:

Undergraduate students
 Components
  % of Final Grade
 Lab Assignment
  15%
 Homeworks
  15%
 Test I
  20%
 Test II
  20%
 Project
  25%
 Discretion
 5%

 
Laboratory Assignments
The lab assignments serve two purposes.  First, they allow the students to apply what is taught during lectures.  After completing all lab assignments the students will have the skills required to complete the main purpose of the lab – the final project. During the first semester the students will design and verify a VLSI circuit using the Mentor Graphics CAD / Cadence tools.

 Lecture Notes

Lecture notes will be available in PPT and PDF format.
The notes may be subject to slightly change.

 

Laboratory Assignments

Lab hours
Lab Session#1: Monday 7:00 - 8:30 PM


Labs Assignments

What
 Who
 Issued
 Due
 Assignment
 LAB #1
  U, G
 8/27/07 9/10/07  LAB #1 (Full Custom VLSI Design -- Inverter Layout)
 LAB #2
  U, G 9/10/07 9/17/07  LAB #2 (Schematic Capture, DC Analysis, Transient Analysis -- Inverter, NAND2)
 LAB #3
  U, G 9/17/07 10/1/07  LAB #3 (Standard Cell Design Flow -- from Schematic to Layout)
 LAB #4
  U, G 9/24/07 10/8/07 Updated Version:
LAB #4 (Standard Cell Design Flow -- from Verilog to Layout)
 LAB #5
 U, G
 10/1/07 10/15/07  LAB #5 (Standard Cell Design Flow -- from VHDL to Layout, Mu0 Processor)
 LAB #6
  U, G 10/1/07 10/22/07  LAB #6 (Power Analysis using Encounter)

Useful CADENCE tutorials


Homeworks


What
 Who
 Issued
 Due
 Assignment
HW #1
  U, G
 9/10/07 9/19/07  HW #1
HW #2  U, G 9/24/07 10/3/07  HW #2
HW #3 
  U, G 10/30/07 11/7/07  HW #3
HW #4  U, G 11/14/07 11/26/07  HW #4

Documents


Links





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