CPE/EE 422/522 - Advanced
Logic Design,
Summer 2003
Course Info
Lecture Notes
Labs
Homeworks
Links
Course Information
Term and Course Credit:
Summer Semester 2003, 3 Credit Hours
Time and Place:
Lecture: MW 5:00 PM - 7:00 PM, Room 207
Instructor:
Dr. Aleksandar Milenkovic
Email: milenka@ece.uah.edu
Office: 217-L
Phone: (256) 824 6830
MW: 7:00 - 8:00 PM
Pan, Zexin
Email: panz@email.uah.edu
Phone: (256) 824-3483
Office: Eb242d
Preston, Chidebelu
Email: chidebp@ebs330.eb.uah.edu
Phone: EB 142
Office: 825-6317
Class Web page:
http://www.ece.uah.edu/~milenka/cpeee_422522_03S
Description:
Advanced concepts in Boolean algebra, use of hardware description languages as
a practical means to implement hybrid sequential and combinational designs,
digital logic simulation, rapid prototyping techniques, and design for
testability concepts. Focuses on the actual design and implementation of
sizeable digital design problems using representative Computer Aided Design
(CAD) tools.
Text Book:
Digital Systems Design Using VHDL, Charles H. Roth, Jr., PWS Publishing, 1998
(ISBN: 0-534-95099-X).
Reference Text:
Fundamentals of Digital Logic with VHDL Design, Stephen Brown, Zvonko Vranesic,
McGraw-Hill, 2000
(ISBN: 0-07-012591-0).
Prerequisite:
EE 202 Introduction to Digital Logic Design
Academic Misconduct:
Academic misconduct of any type will not be tolerated.
Students are expected to conform to the UAH policies concerning academic
misconduct as outlined in Article III (starting on page 91) of the 2000-2001
UAH Student Handbook.
Exam Dates:
Midterm Exam - June 30, 2003
Laboratory Exam - July 21, 2003 - July 25, 2003
Final Exam - July 30, 2003, 6:30 PM -- 9:00 PM.
Grade Policy:
Final course grades will be determined in the manner outlined below:
|
# |
|
% of Final Grade |
|
1 |
Lab Assignments |
55% |
|
2 |
Midterm Exam |
15% |
|
3 |
Final Exam |
30% |
Laboratory Assignments:
The Laboratory Assignment component of the grade will be composed of
simulation, labs, practical exam, and for graduate students a separate graduate
design project. SIMULATIONS represent small assignments which utilize the
Symphony EDA or Altera simulators to demonstrate the functionality of the
design. The LABs represent complete digital designs which are to be actually
implemented on rapid prototyping hardware that is present within the Rapid
Prototyping Laboratory, RPL. The practical EXAM is a short exam which measures
the students ability to implement simple designs using the CAD tools. Graduate
students will be given an additional laboratory assignment (GRAD). The
instructor will supply a default graduate laboratory assignment to the class.
The assignment of credit for each of these components is shown below:
|
Assignment |
Title |
% of the Final Grade |
|
|
|
|
CPE/EE 422 |
CPE/EE 522 |
|
Simulation |
Various Altera and Symphony EDA schematic capture simulations given to support course material. |
10% |
10% |
|
Lab#1 |
4 Bit to Seven Segment Converter |
10% |
10% |
|
Lab#2 |
PS 2, PC keyboard Interface. |
5% |
5% |
|
Lab#3 |
Computer Display Interface. |
10% |
5% |
|
Lab#4 |
Scanning Keypad Interface. |
10% |
5% |
|
Lab Exam |
|
10% |
10% |
|
Graduate Design |
|
|
10% |
Lecture notes
Syllabus (*.doc)
Lab Report Front Page (*.doc)
|
Date |
Topic |
Notes |
Book Chapter |
|
05/28/03 - |
Combinational Logic, Boolean Algebra, |
1.1, 1.2, 1.3, 1.4 |
|
|
06/02/03 |
Combinational-circuit Building Blocks, |
1.5, 3.1, 3.2, 3.3 |
|
|
06/04/03 |
Sequential Networks, Mealy Sequential Networks, |
1.6 – 1.12 |
|
|
06/09/03 |
Sequential Network Timing, Setup and hold times, |
1.8 – 1.12 |
|
|
06/11/03 |
VHDL: Comb. Networks, Flip-flops, |
2.1 – 2.3 |
|
|
06/16/03 |
VHDL: Processes, Sequential Machines, Delays |
2.4 – 2.11 |
|
|
06/18/03 |
|
|
|
|
06/23/03 |
|
2.4 – 2.11 |
|
|
06/25/03 |
Midterm Preparation |
|
|
|
06/30/03 |
|
|
|
|
07/02/03 |
VHDL:
Procedure, Functions, Packages, Libraries |
|
|
|
07/07/03 |
Lab4, VHDL: Attributes, Signal resolution |
8.1 – 8.3 |
|
|
07/09/03 |
VHDL: Attributes, Signal resolution, |
8.4 – 8.7 |
|
|
07/14/03 |
VHDL: Generate, Synthesis, TextIO |
8.6 – 8.9 |
|
|
07/16/03 |
|
8.10 |
|
|
07/21/03 |
Networks for Arithmetic Operations |
|
|
|
07/23/03 |
Networks for Arithmetic
Operations |
|
|
|
07/28/03 - |
|
|
|
Homeworks
Suggested Homework
Assignments:
Students are encouraged to independently or in small groups work the following
homeworks.
Due to the size of the class none of these homeworks will not be taken up and
graded. Complete solutions will be available on the class web site.
|
# |
Assigned |
Due |
Sections in the text |
Problems |
Solutions |
|
1 |
06/04/03 |
06/11/03 |
1, 3 |
||
|
2 |
06/23/03 |
06/27/03 |
1, 2 |
Textbook: 2.1, 2.2, 2.3 |
|
|
3 |
07/09/03 |
|
2 |
Textbook: |
|
|
4 |
|
|
|
|
|
Labs
Rapid Prototyping Laboratory (RPL):
The Rapid Prototyping
Laboratory, RPL, is used extensively in this course to support the
simulation and laboratory design projects. The RPL is a facility that was
partially funded by a grant from the
National Science Foundation to support the introduction of modern Computer
Aided Design, CAD, and rapid prototyping practices in the undergraduate
engineering curriculum. Students will be given open access to this laboratory
during the times when the Engineering Building is open. Each student will be
expected to sign up for at least one preferred access time. This is a two hour
time period when students will be guaranteed access to the laboratory
equipment. This time period will also be used for introductory sessions and the
laboratory exam. The RPL is located in room 226 of the Engineering Building.
References:
Altera's MAX+plus II and the Altera's UP 1
Educational Board, B. Earl Wells, Sin Ming Loo, UAH, August 2001.
Altera University Program Design Laboratory
Package User's Guide, Ver. 1.02, Altera Corporation, November 1999.
Lab hours:
Group #1: Monday 3:00 - 5:00 PM, Mr. Zexin Pan
Group #2: Tuesday 7:00 - 9:00 PM, Mr. Preston,
Chidebelu
Group #3: Wednesday 3:00 - 5:00 PM, Mr. Zexin Pan
Group #4: Wednesday 7:00 - 9:00 PM, Mr. Preston,
Chidebelu
Group #5: Thursday 10:00 - 12:00 AM, Mr. Preston, Chidebelu
Labs Assignments:
|
Assignment |
Title |
Due |
|
|
|
|
|
Altera EDA schematic capture simulations given to support course material |
06/06/2003 |
|
|
4 Bit to Seven Segment Converter |
06/13/2003 |
|
|
Symphony EDA's VHDL Simili VHDL Compiler and
Simulator |
06/20/2003 |
|
|
|
06/27/2003 |
|
|
Computer Display Interface |
07/04/2003 |
|
|
|
07/18/2003 |
|
|
Lab Exam |
|
07/25/2003 |
|
|
07/30/2003 |
Links
- VHDL
- Web Resources on VHDL, FPGA, Circuit Design, etc.: http://www.engr.uky.edu/~huang/websrc.html
- VHDL Tutorial: http://www.vhdl-online.de/
- VHDL Cookbood
- Hyperlinked VHDL-93 BNF Syntax
- Lots of VHDL information (FAQ, introduction, advance use, etc)
- VHDL Synthesis Tutorial
- Behavioral Synthesis
- FPGAs
- Altera Flex 10K Devices
- Xilinx XC9500 CPLD ( .pdf )
- Xilinx Virtex-II FPGA ( .pdf )
- Altera Stratix PLD ( .pdf )
-
- Misc
- Oral Presentation Advice, by Mark D. Hill
- Writing Project Proposals ( .pdf )
- Writing Progress Project Reports ( .pdf )
- Writing Final Project Reports ( .pdf )
-