CPE 626 -
Advanced VLSI Systems,
Fall 2004

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Course Information

Term and Course Credit: Fall Semester 2004, 3 Credit Hours

Time and Place: Lecture: MW 5:30–6:50 PM, EB 229

Instructor: Dr. Aleksandar Milenkovic
Email: milenka@ece.uah.edu
Phone: (256) 824 6830
Office: 217-L

Office Hours: MW 7:00-8:00 PM or by appointment

Class Web page: http://www.ece.uah.edu/~milenka/cpe626-04F

Description:
In the future we will need more customized, application-specific solutions, which can provide the performance needed at a lower cost than general-purpose architectures. Because cost and time-to-market constraints are very important to such systems, architecture should permit automatic design, including high-level architectural design. In this course we will present a new design methodology based on using modern hardware description languages such as VHDL, Verilog, and SystemC. The course addresses algorithm, architecture, and implementation aspects of common building blocks (arithmetic processing elements, filters, processor cores, etc).

Recommended References:

· J. Rabaey, A. Chandarakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective Prentice Hall, 2/e, ISBN 0-13-090996-3.

· Michael John Sebastian Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997. ISBN: 0201500221.http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm

· Peter J. Ashenden, The Designer's Guide to VHDL (2nd edition), Morgan-Kaufmann Publishers, 2002 (ISBN: 1-55860-674-2).

· K. C. Chang, Digital Systems Design with VHDL and Synthesis - An Integrated Approach, IEEE Computer Society, 1999.

Prerequisite: CPE 526

Academic Misconduct: All students will be trusted to pursue their academic careers with honesty and integrity. Academic dishonesty includes, but not limited to, cheating on a test or other course work, plagiarism, unauthorized collaboration with other persons. Academic misconduct of any type will not be tolerated. Students are expected to conform to the UAH policies concerning academic misconduct as outlined in Article III (starting on page 91) of the 2000-2001 UAH Student Handbook.

Exam Dates:
Midterm Exam - October 20 (Wednesday), 2004

Grading Policy:
Final course grades will be determined in the manner outlined below. Grades will be determined on a 70-80-90 straight scale. On occasion I may use a slightly lower scale, but I will never raise the requirements.

#		% of Final Grade
1	Homeworks	20%
2	Midterm	25%
3	Project	35%
4	Essay	15%
5	Class participation	5%

Topics:

· Languages for VLSI synthesis: VHDL, Verilog, SystemC.

· FPGA hardware structures.

· Design and analysis of algorithm-specific VLSI processor architectures. Topics include the implementation of pipelined and systolic processor structure.

· Techniques for mapping numerical algorithms onto custom processor arrays, including Application Specific Instruction Processors (ASIPs).

· Prototyping using Xilinx ISE and Xilinx FPGAs.

· High-level DSP algorithm simulation and code generation.

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